These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. When the enable is taken LOW the output will be latched at the level of the data that was set up. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.
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At an output "1" level of 2. On the other hand, the output "1" level of 74LS latch does not go to Vqc without an external pull-up resistor. In order to better approximate the COP output characteristics, add a 74C buffer to the output of the 74LS , thus. Upon power up, the K74CF will stabilize with the last output state valid before power down.
The non-volatile storage and recall. The timing of D port data is then ,. Using the set-up as shown in Figure 4, at an output "0 " level of 0.
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